In June 2026, TSMC announced it would triple its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity by 2028, at a capital cost exceeding $15 billion. The announcement barely registered outside semiconductor circles. It should have been front-page news. CoWoS is the manufacturing process behind every NVIDIA H100, H200, and Blackwell GPU — the chips powering the AI boom. And TSMC can’t build the packaging capacity fast enough.
The industry spent fifty years obsessing over transistor shrinks. The next decade will be decided by packaging — how chips are assembled, connected, and integrated. The moat has moved.
When Moore’s Law stopped paying
The economics of transistor scaling broke down around the 5-nanometer node. Each successive shrink now costs more per transistor than the last — a reversal of the historical pattern that powered the industry’s growth. TSMC’s 3nm process, while technically triumphant, offers diminishing performance-per-dollar improvements over 5nm. The 2nm node, entering risk production in 2026, continues this trend: better, but not transformative, and enormously expensive.
Advanced packaging sidesteps this problem entirely. Instead of making transistors smaller, it connects multiple chips — processors, memory, accelerators — into a single package with ultra-high-bandwidth interconnects. NVIDIA’s Blackwell architecture doesn’t rely on a single massive die. It combines two reticle-sized GPU dies with eight high-bandwidth memory stacks, all integrated through TSMC’s CoWoS packaging. The performance gains come from the integration, not the shrink.
The numbers are striking. AMD’s MI300X, which uses advanced 3D stacking to integrate CPU, GPU, and memory, delivers 1.6x the AI performance per watt of its predecessor — with most of the improvement attributable to packaging architecture rather than process node advances. Broadcom’s custom AI accelerators for Google and Meta rely heavily on 2.5D integration to achieve their performance targets.
This shift has profound implications for where value accrues in the semiconductor supply chain.
The new chokepoints
Advanced packaging has created bottlenecks as severe as any in the industry’s history — and far less appreciated by investors.
TSMC controls an estimated 80% of global CoWoS capacity. The company’s packaging revenue, negligible five years ago, exceeded $8 billion in 2025 and is projected to surpass $15 billion by 2027, according to company disclosures and analyst estimates. Every major AI chip — NVIDIA, AMD, Broadcom’s custom designs, even Intel’s Gaudi accelerators — depends on TSMC packaging capacity.
But TSMC is not the only chokepoint. The ABF (Ajinomoto Build-up Film) substrate market, critical for high-performance packaging, is dominated by three Japanese companies: Ajinomoto, Ibiden, and Shinko Electric. When substrate shortages constrained GPU production in 2023-2024, it wasn’t wafer capacity that limited output — it was packaging materials.
High-bandwidth memory (HBM) represents another constraint. SK Hynix and Samsung control over 90% of HBM production, and HBM3E — the current generation — requires manufacturing precision that only these two companies have mastered. Micron is ramping HBM production but remains 18-24 months behind. Every AI accelerator needs HBM. There is no substitute.
The OSATs (outsourced semiconductor assembly and test providers) — ASE Technology, Amkor, JCET — are investing heavily to capture advanced packaging demand that TSMC can’t serve. ASE, the world’s largest OSAT with $18 billion in 2025 revenue, has committed $3 billion to advanced packaging capacity through 2027. But the most advanced processes (CoWoS, SoIC) remain TSMC-exclusive, giving the foundry a structural advantage that OSATs cannot easily replicate.
The investment implications
The packaging shift redistributes semiconductor profit pools in ways most investors haven’t priced in.
First, equipment makers serving the packaging segment are growing faster than those serving front-end wafer processing. Applied Materials’ packaging-related revenue grew 35% in fiscal 2025, versus 12% for its overall semiconductor systems group. Disco Corporation, the Japanese maker of dicing and grinding equipment essential for advanced packaging, saw its stock triple between 2023 and 2026. BE Semiconductor, a Dutch packaging equipment specialist, has become one of Europe’s best-performing tech stocks on the same thesis.
Second, the foundry business model is evolving. TSMC’s packaging revenue carries higher margins than its wafer fabrication business — estimated at 55-60% gross margin versus 53% for the company overall. As packaging becomes a larger share of revenue, TSMC’s profitability structurally improves. This is not reflected in valuations that still treat TSMC as a pure-play foundry.
Third, fabless companies’ competitive positions increasingly depend on packaging access, not just chip design. NVIDIA’s moat is not just its CUDA software or its chip architectures — it is its guaranteed allocation of TSMC CoWoS capacity, secured through multi-billion-dollar prepayments. A competitor with a better chip design but no packaging allocation cannot ship product. The supply chain is the strategy.
The counterargument: packaging is a commodity
Skeptics argue that advanced packaging will commoditize like every semiconductor manufacturing step before it. Today’s CoWoS bottleneck, they contend, is a temporary capacity mismatch, not a structural moat. As ASE, Amkor, Samsung, and Intel all ramp competing packaging technologies, TSMC’s pricing power will erode. The history of semiconductors is the history of bottlenecks dissolving under competitive investment.
This view underestimates the technical barriers. CoWoS requires co-optimization of design, wafer processing, and packaging — capabilities that exist in exactly one company at scale. Samsung has announced competing offerings but has not demonstrated equivalent yields. Intel’s Foveros 3D stacking is promising but serves primarily Intel’s own products. The learning curve in advanced packaging, measured in years and billions of dollars, is as steep as in leading-edge wafer fabrication.
More fundamentally, the skeptic’s case ignores the systems dimension. Advanced packaging is not a standalone manufacturing step — it is co-designed with the chip architecture. NVIDIA’s engineers design Blackwell knowing exactly what TSMC’s CoWoS can and cannot do. That co-design relationship, built over a decade, cannot be replicated by switching to a different packaging vendor. The moat is the integration, not just the capacity.
What to watch
Three signals will determine how this plays out. First, TSMC’s CoWoS capacity additions through 2028 — if the company hits its tripling target, the bottleneck eases but TSMC’s revenue grows enormously. If it falls short, AI chip supply remains constrained and pricing power intensifies.
Second, the emergence of alternative packaging ecosystems. Intel’s foundry ambitions depend critically on offering competitive advanced packaging to external customers. Samsung’s success or failure in winning CoWoS-like orders from NVIDIA or AMD would signal whether TSMC’s moat is truly unassailable.
Third, the shift to 3D stacking (SoIC, hybrid bonding) for logic-on-logic integration. This is the next frontier beyond 2.5D — stacking processor dies directly atop each other rather than side-by-side on an interposer. TSMC leads here too, but the technology is earlier-stage and the competitive field more open.
The transistor shrink defined fifty years of semiconductor investing. The winners were those who bet on the companies pushing Moore’s Law forward. The next decade belongs to those who understand that the action has moved — from making transistors smaller to connecting chips smarter. The packaging play is not a side bet. It is the main event.
TSMC is spending $15 billion to triple packaging capacity. That number tells you everything about where the industry’s center of gravity has shifted.
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